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Is it possible to use an interrupt controller based on the Generic Interrupt Controller (GIC) architecture in a device built around a single core Cortex-A9 MPCore processor?
Which of the following is an accurate description of network storage as compared to on-chip RAM?
In an MPCore system, when one core is waiting for resources to be released, what instruction could be used to reduce that core's power consumption?
In a single-processor system, which of these operations requires a barrier instruction to guarantee correct operation?
Using a Generic Interrupt Controller (GIC), when the interrupt handler writes to the End of Interrupt Register (ICCEOIR), which of the following state transitions might occur for that interrupt ID?
In an ARMv7-A processor that includes the Advanced SIMD extension (NEON), where are the data values operated on by NEON instructions stored?
The following pair of functions implement a simple mutex spinlock which might be used to protect a critical code section in a multi-threaded application. The address of the lock variable is in r0.
In order to minimize power while waiting for the lock to be available. SEV and WFE instructions can be used to place the processor in a low power state while waiting for the lock to become available. At which points should these instructions be placed?
Which of the following register values would cause an unaligned access when the instruction LDRH r0, [r1] is executed?
A deeply embedded real-time industrial control system is missing some hard real-time interrupt deadlines. Which of the following performance analysis techniques is the most suitable for identifying which routines are causing the problem?
In an ARMv7 processor that includes the Advanced SIMD (NEON) extension, how many single precision floating point values can be stored in the Q0 register?
A message passing system between two CPUs is implemented using data stored in a shared area of memory. To pass a message, the first CPU executes the instructions:
The second CPU receives the message using the instructions:
On both CPUs, r1 = 0x5000 and r2 = 0x6000. At which of the points A, B, C and D must Data Memory Barrier (DMB) instructions be placed in order to ensure messages are passed reliably and efficiently?
Which of the following best describes the relationship between Tightly Coupled Memories (TCM), Level 1 (L1) and Level 2 (L2) cache memory systems?
A function written in C has the prototype:
void my_function(float a. double b, float c);
The function is built and linked into an application using hard floating-point linkage. What registers are used to pass arguments to the function?
In a Cortex-A processor, assume an initial value of R1 =0x80004000.
If the following instruction causes a data abort, what value will R1 contain on entry to the abort handler?
LDR R0, [R1, #8]!
Assuming a 4-core Cortex-A9 SMP system which does not use the Accelerator Coherency Port (ACP). and operates the L1 caches in writeback mode, in which of the following situations is a cache clean operation required?
In the VFPv4-D32 architecture, which of the following best describes the arrangement of the registers?
Which power mode describes the state where the ARM processor is powered down, but its Level 1 caches remain powered?
Which TWO of the following interrupt types does a Generic Interrupt Controller (GIC) support? (Choose two)
Which of the following techniques can be used to obtain a precise count of clock cycles when profiling software over an arbitrarily long period of time using the Performance Monitoring Unit?
Which one of the following features must any processor support to conform to the ARMv7-A architecture?
In an experiment, the time taken for an application to complete a given task is measured using a stopwatch. Which THREE of the following make up the total time? (Choose three)
The disassembly of a program written in C shows calls to the function__aeabi_fadd. Which one of these compiler floating point options could have been used?
The Cortex-A9 processor has 6 breakpoint units and 4 watchpoint units. What is the maximum number of breakpoints the debugger can set on code in ROM?
A program running on a development board that is connected to a host using a debugger can access a file on the host by using:
When programming in C, how many bytes of stack are needed to pass parameters when calling the following function?
int foo( int arg_a, int arg_b, int arg_c )
A C code segment contains three calls to a function, foobar ().
This code segment is to be linked with a static library that defines foobar ().
Ignoring inlining, how many copies of foobar () will the ARM linker place in the output?
In an ARMv7-A processor with Security Extensions, which of the following mechanisms best describes the way Secure memory is protected from access by software running in a Non-secure privileged mode?
Under which of the following data-sharing scenarios would cache maintenance operations be necessary?
Which of the following memory attributes, specified in a translation table entry, could be used to protect a page containing a read-sensitive peripheral from speculative instruction fetches?
Which of the following statements regarding Strongly-ordered memory is architecturally FALSE?
In a Cortex-A processor, after which TWO of these events is a cache maintenance operation required to ensure reliable code execution? (Choose two)
In which of these cases would code have better performance when compiled for Thumb state than when compiled for ARM state?
An application contains three calls to an external function, foobar(), which is defined in a shared (or dynamic) library. How many copies of foobar() will the linker place in the application image?
(Ignore linker inlining)
In an operating system environment, most applications are executed in which processor mode?
When a linker is removing unused sections during a static link (for example, -remove or -gc-sections), it finds the sections to keep by following all relocations starting from:
Which of the following sequences of stages comprise the ARM7TDMI three-stage pipeline?
In which of the following situations would you use a mutex to avoid synchronization problems?
Assume a Big-Endian (BE) memory system with the following memory contents.
Byte Address Contents
0x100 0x11
0x101 0x22
0x102 0x33
0x103 0x44
If R5 = 0x100, what are the contents of R4 after performing the following operation?
LDR R4, [R5]
An undefined instruction will cause an Undefined Instruction exception to be taken when:
Which of the following will cause the ARM Compiler to target the Thumb instruction set?
Which one of these statements is TRUE about code running on final hardware without a debugger attached?
When applied to locations in memory configured using a write-back cache strategy, what does a data cache 'clean' operation do?
Consider the following code sequence, executing on a processor which implements ARM Architecture v7-A.
LDR r0, [r1]
STR r0, [r2]
STR r3, [r3]
R1 points to a location in normal memory. R2 and R3 point to device memory.
Which of the following statements best describes the ordering rules which apply to this sequence?
To return from a Data Abort handler and re-execute the aborting instruction, what value should be loaded to the PC?
When setting the initial location of the stack pointer and the base address of the heap, the ARM EABI requires that the:
When using the ARM Compiler (armcc), which of the following possible keywords can be used to remove padding bytes from a structure?
Which of the following ARM processors has the best energy efficiency (measured in mW/MHz)?
When the processor is executing in Thumb state, which of the following statements is correct about the values stored in R15?
What will be the contents of R2 after the execution of the following piece of code?
LDRR1, =0xAABBCCDD
MOV R2, #0x4
ANDSR1, R1, #0x4
ADDNE R2, R2, #0x4
Which THREE of the following items should be preserved by software when entering dormant mode? (Choose three)
TESTED 23 Nov 2024